1. Field of the Invention
This invention relates to fabrication of III-V semiconductor devices having an active region, and, more particularly, to a post-ion implantation annealing technique to remove implantation damage in the device active region.
2. Description of the Prior Art
Currently, two approaches to GaAs integrated circuit (IC) technology used in the industry include mesa technology with a recessed gate and planar technology with multiple, localized ion implantations. The mesa with recessed gate technology suffers from ultimate density and yield limitations associated with the mesa structures. Thus, the main application of this technology has only been directed towards ultra high speed, medium scale integration (MSI) circuits and ultra low power, enhancement mode field effect transistor (ENFET) logic. The planar technology, with multiple localized ion implantation, has been applied successfully to fabricate large scale integrated (LSI) circuits with 1,000 gate chips on chromium-doped substrates. The process involves ion implantation through an encapsulation dielectric, which is subsequently used as an annealing encapsulation, and a metal lift-off vehicle. The process is suitable for multiple metal layered structures. However, there are inherent problems associated with dielectric encapsulation annealing. Dielectric encapsulation exerts a significant stress at the GaAs interface, which in turn induces significant migration of background Cr and other impurities during high temperature annealing. As a result, the semi-insulating, or high resistivity, GaAs substrate becomes conductive, resulting in poor inter-device isolation. To cope with this Cr migration problem, the annealing temperature must be kept sufficiently low (below about 860.degree. C.), and stringent material qualification processes and tight process controls on the dielectric encapsulant must be used, to some degree resulting in yield losses.